Methods for Handling Spare Cell Placement in Physical Compiler

Posted at 07月 16, 2010

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Methods for Handling Spare Cell Placement in Physical Compiler

Question:

Dealing with Spare Cells in Physical Compiler

Answer:

Many current ASIC design methodologies employ the use of spare
cells somewhere in the design implementation flow. One primary
reason for inserting spare cells is to allow metal-only changes
to a design to fix functional and/or timing problems discovered
late in the design cycle, thereby saving dollars that would otherwise
be spent scrapping prefabricated silicon and delaying product schedules.

Spare cells pose a unique challenge to design engineers and their
CAD support in that numerous spare cell methodologies are in active
use in the field today. Choosing a spare cell methodology to satisfy a
design’s needs and understanding the implications of that particular
methodology on the entire design flow can be an ongoing challenge.

This article attempts to document how Physical Compiler supports
various widely used spare cell methodologies. This document is a living
document. From time to time as new information is obtained, new
methodologies are highlighted, and existing methodologies (documented
herein) change, this document will be updated.

This article is by no means an all-inclusive article. It is intended to
be a starting point in developing or enhancing a spare cell flow when
you use the Synopsys physical synthesis tools.

In addition to the methods outlined below, as of the 2002.05 release,
Physical Compiler supports the “insert_spare_cell” command. More information
about this command is available in solvit article:
http://solvnet.synopsys.com/retrieve/900090.html

Following are example methods that can be employed starting
with Physical Compiler v1.22. Some methods are more detailed
than others. You can see that you have flexibility in how the spare
cells can be handled. Depending on the availability of resources,
you can combine multiple methods.

The methods are
o Traditional Method (two flows: FLOW 1 and FLOW 2)
o Gridded Placement Method (FLOW 3)
o Grouping Method (Regions) (FLOW 4)
o General Clumped Method
o Preplaced Spare Cells
o Pseudo-Random Placement (FLOW 5)

Traditional Method
==================
Notes:
o Spare cells are placed in the routing tool.
o Add cells later or dont_touch a subblock with no pins.

The basic premise of this method is to minimize changes to a pre-
existing design flow. The basic idea is to handle the spare cells in
the traditional place and route tool (which is now primarily a
routing tool).

The two traditional flows are FLOW 1 and FLOW 2.

FLOW 1:
Goal: The design is optimized and placed; it contains
spare cells but spare cells are not placed.

1. Design has hierarchy.
2. Spare cells are instantiated in a submodule (or submodules).
3. Spare cell submodules do not have PORTS (no I/O connections).
4. Spare cell submodules have the ‘dont_touch’ attribute applied.
5. Optimize and place the design (physopt).
6. Write the placement (write_pdef / db2def5).
7. Read the placement into the router.
8. Place only spare cells (with other cells fixed in place).
9. Continue with clock tree synthesis and routing.

Physical Compiler (v1.2x) does not recognize the cells in the
submodules because there is no functional or tieoff path to the
cells. The result of this flow is a design with all cells
optimized and placed except for the spare cells. The spare
cells remain but are not placed. This process results in a
partially placed PDEF/DEF file that is sent to the router.

Before routing takes place, one extra step must take place in the
router–place the spare cells. This must be done with the preplaced
(within Physical Compiler) nonspare cells set to FIXED so that they
are not moved; otherwise, critical path timing might be negatively
affected.
Placement can be fixed in Physical Compiler with the
set_dont_touch_placement command, or there are typically optional
settings in the router to control this. If spare cells are not placed,
the router generates errors when a route is attempted. If no spare cells
are sequential devices, it might be possible to place the spare cells
after clock tree synthesis; otherwise, place them before clock tree
synthesis so that clock tree synthesis takes into account the
locations of the sequential cells.

If Physical Compiler is used in a multipass environment, care must be
taken to ensure that the spare cell submodules are not ungrouped between
passes. If they are ungrouped and end up at the top level, Physical
Compiler will re-place these cells in the subsequent run, which might not
be your intent.

See Appendix A for sample Verilog code for FLOW 1.

The following flow highlights a case where spare cells are added
to the netlist in the router.

FLOW 2:
Goal: The design is optimized and placed; there are no spare
cells in netlist

1. Optimize and place the design (physopt).
2. Write the placement (write_pdef / db2def5).
3. Read the placement results into router.
4. Insert spare cells in the router.
5. Place only spare cells (other cells are locked in place).
6. Continue with clock tree synthesis and routing.

NOTE:
This flow has not been tested and might cause difficulties
during the back-annotation phase (because the netlist has changed
in the routing tool and is not identical to the original).

Gridded Placement Method
===========================
The gridded placement method (FLOW 3) is similar to FLOW 1 except for the
steps that place spare cells.

FLOW 3:
Goal: The design is optimized and placed; spare cells
are post-placed within Physical Compiler in a gridded
fashion.

1. The design has hierarchy.
2. Spare cells are instantiated in a submodule (or submodules).
3. Spare cell submodules do not have PORTS (no I/O connections).
4. Spare cell submodules have the ‘dont_touch’ attribute applied.
5. Optimize and place the design (physopt).
6. OPTIONALLY apply dont_touch_placement to all cells except
spare cells.
7. Run a script (available in Appendix A) to make spare cells visible and
legal Physical Compiler (modifies spare cell modules).
8. Place spare cells Physical Compiler (legalize_placement -eco).
9. Run a script (available in Appendix A) to revert changes made to spare
cell modules.
10. Write placement (write_pdef / db2def5).
11. Send the placement result to the router.

Steps 1 through 6 result in an optimized placement of the design
with only the spare cells unplaced. This is because the placement
engine does not recognize the spare cells in the spare cell submodules
(no net connections are made to these modules). The steps 6
through 8 are required to add a port to the spare cell modules
(make the spare cells visible to Physical Compiler) and to remove all
connections within the spare cell module (to satisfy legalize_eco
requirements). These steps can be encapsulated in a procedure
call. Step 9 reverts all changes made in Step 7 so the original netlist
is retained.

*Note:
A ‘legally’ instantiated cell falls into one of the following
categories:

A. Instantiated, dont_touched, and completely unconnected at the
top-level
B. Instantiated in a submodule, completely unconnected. The
submodule is dont_touched and spare cells are dont_touched.
C. Instantiated, dont_touched, connected to a functional net of
the design (anywhere in hierarchy).

Grouping Method (Regions)
=========================
This method (FLOW 4) uses a ‘physical’ command–set_bounds–that assigns
cells to specific regions in the design’s floorplan. The set_bounds
command is requires a list of cells as well as a bounding box (two pairs
of [x,y] coordinates) to define the desired placement area.

FLOW 4:
Goal: The design is optimized and placed; spare
cells are placed in predefined areas.

1. Spare cells are legally instantiated and visible to Physical Compiler.
2. Identify areas where spare cells are to be placed.
3. Specify set_bounds to assign groups of cells to areas identified
in Step 2. For example,
set_bounds -coord {100 100 200 200} [find design "*spare*"]
4. Optimize and place the design(physopt).
5. Write the placement (write_pdef / db2def5).
6. Send the placement results to the router.

General Clumped Method
======================
This method allows Physical Compiler to place (during the physopt or
compile_physical process) spare cells without any predefined placement
constraints. The spare cells in a block are not in a critical timing
path, they are automatically placed in the same area as the cells in
the parent block of the spare cells.

The spare cells must be legally instantiated (see the note in the Gridded
Placement Method for the definition) before optimization. The spare cell
submodules must have dont_touch attributes applied.

Preplaced Spare Cells Method
============================
In general, any type of cell can be preplaced in the
floorplanning stage. This method takes advantage of preplacing
cells in a floorplanner to specify and lock down locations for
spare cells. When the floorplan is loaded into Physical Compiler,
the spare cells are already fixed in place. A caveat: This can have
unpredictable affects on critical path timing.

Pseudo-Random Placement Method
==============================
This method (FLOW 5) uses the rand() Tcl function to randomly spread the
spare cells across the floorplan. In this case, the cells were
intially placed in the bottom right corner, as can be seen by the
empty space that was left when they were re-placed randomly. This
method uses the manual placement command with a random seed for
the location. Cell placement must be legalized following the
random placement because of the possibility of overlapping cells.

FLOW 5:
Goal: The design is optimized and placed; spare
cells are placed in pseudo-random locations.

1. Run physopt with spare cells not visible to Physical Compiler
(that is, in an unconnected submodule).
2. Make spare cells visible to Physical Compiler.
3. Identify overall area (rectangular coordinates) where spare
cells are to be randomly placed.
4. Run a script (available in Appendix A) to randomly place cells.
5. Write placement (write_pdef / db2def5).
6. Send the placement results to the router.

Appendix A: Scripts
====================

Sample Verilog code for FLOW 1
——————————

Notice there are no ports in this code.

module spare_cell_0 ( );
wire net5, net2, net14, net3, net12, net4, net10, net6, net8,
net1, net9, net0, net11, net7;
sdffprs_4 z_cell_spare_sdffprs_4 ( .q(net1), .qb(net2), .sb(1′b1),
.d(net0), .ck(1′b0), .sdi(net9), .se(1′b0), .rb(1′b0) );
buf_16 z_cell_spare_buf_16_1 ( .x(net3), .a(net1) );
inv_16 z_cell_spare_inv_16_2 ( .x(net8), .a(net7) );
inv_8 z_cell_spare_inv_8 ( .x(net0), .a(1′b0) );
nand3_8 z_cell_spare_nand3_5_1 ( .x(net5), .a(net3), .b(net4),
.c(net14) );
nor3_8 z_cell_spare_nor3_5 ( .x(net7), .a(net6), .b(net10), .c(net12) );
slatpr_8 z_cell_spare_latpr_8 ( .q(net10), .qb(net11), .sout(net12),
.soutb(net14), .rb(1′b0), .d(1′b0), .gb(1′b0), .sdi(1′b0),
.se(1′b0) );
buf_16 z_cell_spare_buf_16_2 ( .x(net4), .a(net2) );
inv_16 z_cell_spare_inv_16_1 ( .x(net6), .a(net5) );
nand3_8 z_cell_spare_nand3_5_2 ( .x(net9), .a(net8), .b(net11),
.c(1′b0) );
endmodule

The previous code segment is an example of a module that the
placement engine will not ’see’. The cells within this module
will not be placed by the placer. In this example, all the spare
cells are connected to one another.

Sample Tcl Script for FLOW 3
—————————-

set symbol_library library/symbol.sdb
set search_path [concat $search_path library . ]
set target_library [list target.db ]
set link_library [concat "*" $target_library]
set physical_library physical.pdb

read_db Top.Floorplanned.db
current_design Top
link
# don’t touch the spare cell modules
set_dont_touch [find cell *spare*] true
uniquify
source constraints.tcl
set physopt_pnet_complete_blockage_layer_names “metal1 metal2″
# file that will hold commands used to restore the spare cell
# connectivity:
set tmpfile “tmp_”
append tmpfile [pid]

proc prepare_spare_cells { _designs } {
global tmpfile
set cur_design [current_design]
redirect $tmpfile {echo “# beginning of script “}
foreach_in_collection a_design $_designs {
redirect -append $tmpfile {echo “\n” }
redirect -append $tmpfile {echo “current_design” \
[ get_object_name $a_design]}
current_design $a_design
create_port BOGUS -direction in
foreach_in_collection a_net [ get_net "*" ] {
redirect -append $tmpfile {echo “create_net” [ get_object_name $a_net] }
foreach_in_collection a_pin [ find pin [ all_connected $a_net ]] {
redirect -append $tmpfile {echo “connect_net” [get_object_name $a_net]\
[get_object_name $a_pin ] }
}
echo “disconnect net:”
disconnect_net $a_net -all ;
echo “remove net:”
remove_net [ get_object_name $a_net ]
}
}
redirect -append $tmpfile {echo “current_design \$cur_design “}
current_design $cur_design
}

current_design Top
link
physopt
echo “placement of cells after physopt, spare cells not placed”
report_cell -physical [ find cell -hier *spare* ]
# make spare cells legally instantiated in design so placer will
# place them: Note cells are called “*spare*”
prepare_spare_cells [ find design *spare* ]
link
legalize_placement -eco
# reconnect spare cells:
source -echo -verbose $tmpfile

write -format db -hier -o spare.placed.db
write_pdef -v3.0 -o spare.placed.pdef
quit

————————————————————————–
Sample Tcl Script for FLOW 5

#Pseudo-random placement Tcl script:

# find placement boundaries:
set bbox_list [get_placement_area]
set min_x [lindex $bbox_list 0]
set min_y [lindex $bbox_list 1]
set max_x [lindex $bbox_list 2]
set max_y [lindex $bbox_list 3]

set delta_x [expr $max_x - $min_x]
set delta_y [expr $max_y - $min_y]

set spare_cells [get_cell -hier *spare*]
foreach_in_collection sp_cell $spare_cells {
set rand_x [expr int([expr rand() * $delta_x + $min_x ])];
set rand_y [expr int([expr rand() * $delta_y + $min_y ])];
set rand_x [expr $rand_x * 1.0 ];
set rand_y [expr $rand_y * 1.0 ];
echo “$rand_x $rand_y”;
set_cell_location -coordinate [list $rand_x $rand_y ] $sp_cell;
# <-MANUAL COMMAND
report_cell -physical $sp_cell; # <- verify it was placed
}

Former article name: Physical_Synthesis-115

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